Model { Name "calib_micoffset" Version 7.8 MdlSubVersion 0 GraphicalInterface { NumRootInports 1 Inport { BusObject "" Name "FromAnalogy" } NumRootOutports 3 Outport { BusObject "" BusOutputAsStruct "off" Name "chirpsignal" } Outport { BusObject "" BusOutputAsStruct "off" Name "volts_in" } Outport { BusObject "" BusOutputAsStruct "off" Name "ToAnalogy" } ParameterArgumentNames "" ComputedModelVersion "1.1362" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" FPTRunName "Run 1" MaxMDLFileLineLength 120 Created "Wed Jan 04 17:33:04 2012" Creator "Adrien" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "xenomai" ModifiedDateFormat "%" LastModifiedDate "Wed Mar 16 17:45:42 2016" RTWModifiedTimeStamp 379273112 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowDesignRanges off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse off ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.11.1" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 2 Version "1.11.1" StartTime "0.0" StopTime "inf" AbsTol "auto" FixedStep "Ts" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" ConcurrentTasks off Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.11.1" Decimation "decim" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "lastbuffer_samps_rnd" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging off DSMLogging off InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "BooleansAsBitfields" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off UseIntDivNetSlope off UseFloatMulNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage off BufferReuse off EnhancedBackFolding off StrengthReduction off ExpressionFolding off BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs off RollThreshold 1 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero off NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "On" AccelVerboseBuild off AccelParallelForEachSubsystem on } Simulink.DebuggingCC { $ObjectID 5 Version "1.11.1" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "none" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "warning" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" FrameProcessingCompatibilityMsg "warning" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "Warning" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" SFUnconditionalTransitionShadowingDiag "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.11.1" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Zero" ProdEndianess "LittleEndian" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "Intel->x86/Pentium" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.11.1" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 8 Version "1.11.1" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateSLWebview" Cell "GenerateCodeMetricsReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly on MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "On" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.11.1" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "InsertPolySpaceComments" Cell "MATLABFcnDesc" Cell "CustomSymbolStrFcnArg" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.11.1" Array { Type "Cell" Dimension 16 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "PortableWordSizes" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "GeneratePreprocessorConditionals" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" CodeExecutionProfiling off ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on ConcurrentExecutionCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" ExtraOptions "-aGenerateTraceInfo=0 -aIgnoreTestpoints=0 " CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 548, 117, 1511, 717 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType DiscreteTransferFcn Numerator "[1]" Denominator "[1 0.5]" InputProcessing "Elements as channels (sample based)" InitialStates "0" SampleTime "1" a0EqualsOne off NumCoefMin "[]" NumCoefMax "[]" DenCoefMin "[]" DenCoefMax "[]" OutMin "[]" OutMax "[]" StateDataTypeStr "Inherit: Same as input" NumCoefDataTypeStr "Inherit: Inherit via internal rule" DenCoefDataTypeStr "Inherit: Inherit via internal rule" NumProductDataTypeStr "Inherit: Inherit via internal rule" DenProductDataTypeStr "Inherit: Inherit via internal rule" NumAccumDataTypeStr "Inherit: Inherit via internal rule" DenAccumDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow off StateMustResolveToSignalObject off RTWStateStorageClass "Auto" } Block { BlockType Gain Gain "1" Multiplication "Element-wise(K.*u)" ParamMin "[]" ParamMax "[]" ParamDataTypeStr "Inherit: Same as input" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Saturate UpperLimitSource "Dialog" UpperLimit "0.5" LowerLimitSource "Dialog" LowerLimit "-0.5" LinearizeAsGain on ZeroCross on SampleTime "-1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" SFBlockType "NONE" Variant off GeneratePreprocessorConditionals off } Block { BlockType Sum IconShape "rectangular" Inputs "++" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on AccumDataTypeStr "Inherit: Inherit via internal rule" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Switch Criteria "u2 >= Threshold" Threshold "0" InputSameDT on OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit via internal rule" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on ZeroCross on SampleTime "-1" AllowDiffInputSizes off } Block { BlockType TransportDelay DelayTime "1" InitialOutput "0" BufferSize "1024" FixedBuffer off TransDelayFeedthrough off PadeOrder "0" } } System { Name "calib_micoffset" Location [1, 79, 1599, 871] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" ReportName "simulink-default.rpt" SIDHighWatermark "372" Block { BlockType Inport Name "FromAnalogy" SID "140" Position [185, 133, 215, 147] BackgroundColor "gray" IconDisplay "Port number" SamplingMode "Sample based" } Block { BlockType Gain Name "Amplitude" SID "344" Position [820, 637, 855, 673] ZOrder -8 NamePlacement "alternate" Gain "Ampl_chirp" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Amplitude F" SID "339" Position [640, 207, 675, 243] ZOrder -8 NamePlacement "alternate" Gain "Ampl_chirp_F" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Amplitude U" SID "372" Position [630, 137, 665, 173] ZOrder -8 NamePlacement "alternate" Gain "Ampl_chirp_U" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Amplitude1" SID "371" Position [640, 292, 675, 328] ZOrder -8 NamePlacement "alternate" Gain "Ampl_chirp" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Chirp" SID "345" Ports [0, 1] Position [640, 680, 680, 720] NamePlacement "alternate" LibraryVersion "1.714" SourceBlock "dspsrcs4/Chirp" SourceType "Chirp" sweep "Linear" mode "Unidirectional" f0 "fstart" f1 "fstop" t1 "sweep_time" Tsweep "sweep_time" phase "pi/2" Ts "Ts" spf "1" datatype "Single" } Block { BlockType Reference Name "Chirp2" SID "340" Ports [0, 1] Position [555, 205, 595, 245] NamePlacement "alternate" LibraryVersion "1.714" SourceBlock "dspsrcs4/Chirp" SourceType "Chirp" sweep "Linear" mode "Unidirectional" f0 "fstart" f1 "fstop" t1 "sweep_time" Tsweep "sweep_time" phase "pi/2" Ts "Ts" spf "1" datatype "Double" } Block { BlockType Constant Name "Constant" SID "346" Position [585, 644, 610, 666] ZOrder -4 NamePlacement "alternate" Value "10" } Block { BlockType Constant Name "Constant1" SID "347" Position [710, 630, 730, 650] ZOrder -4 NamePlacement "alternate" Value "0" } Block { BlockType Saturate Name "Saturation\nfor LS\nprotection" SID "146" Ports [1, 1] Position [940, 140, 970, 170] ZOrder -15 BackgroundColor "lightBlue" InputPortMap "u0" UpperLimit "maxoutputvoltage" LowerLimit "-maxoutputvoltage" } Block { BlockType Switch Name "Switch" SID "348" Position [750, 635, 800, 675] ZOrder -18 NamePlacement "alternate" Threshold "1" InputSameDT off SaturateOnIntegerOverflow off } Block { BlockType TransportDelay Name "Transport\nDelay" SID "349" Ports [1, 1] Position [640, 643, 675, 667] ZOrder -10 NamePlacement "alternate" DelayTime "sweep_time" BufferSize "8" } Block { BlockType SubSystem Name "loudspeaker (&)\naccounting\nfilters (fb&ff)" SID "353" Ports [3, 1] Position [820, 135, 885, 175] BackgroundColor "lightBlue" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "loudspeaker (&)\naccounting\nfilters (fb&ff)" Location [75, 321, 772, 711] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Pfb" SID "354" Position [45, 28, 75, 42] IconDisplay "Port number" } Block { BlockType Inport Name "U_calc" SID "355" Position [45, 118, 75, 132] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "FLS" SID "368" Position [45, 203, 75, 217] Port "3" IconDisplay "Port number" } Block { BlockType Gain Name "Mms/Sd" SID "356" Position [95, 99, 145, 151] BackgroundColor "lightBlue" Gain "Mms/Sd" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum1" SID "357" Ports [2, 1] Position [510, 115, 530, 135] ShowName off FontSize 14 IconShape "round" Inputs "-+|" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum3" SID "367" Ports [2, 1] Position [325, 115, 345, 135] ShowName off FontSize 14 IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "U210V1" SID "359" Position [545, 100, 580, 150] BackgroundColor "lightBlue" Gain "Re/Bl" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off Port { PortNumber 1 Name "VLS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "discrete\nderivative" SID "361" Ports [1, 1] Position [240, 107, 300, 143] ZOrder -4 BackgroundColor "lightBlue" LibraryVersion "1.256" SourceBlock "simulink/Discrete/Discrete Derivative" SourceType "Discrete Derivative" gainval "1.0" ICPrevScaledInput "0.0" InputProcessing "Inherited" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit via internal rule" OutputDataTypeScalingMode "Inherit via internal rule" OutDataType "fixdt(1, 16)" OutScaling "2^-10" LockScale off RndMeth "Floor" DoSatur off } Block { BlockType Gain Name "div. amp.gain factor" SID "362" Position [600, 107, 615, 143] ZOrder -8 BackgroundColor "lightBlue" NamePlacement "alternate" Gain "1/amp_gain_factor" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType DiscreteTransferFcn Name "lead-lag\ncompensator" SID "363" Position [165, 107, 225, 143] ZOrder -2 BackgroundColor "lightBlue" Numerator "cell2mat(HLL_d.num)" Denominator "cell2mat(HLL_d.den)" SampleTime "Ts" } Block { BlockType Gain Name "uncoupling\nFB controller" SID "364" Position [450, 15, 495, 55] ZOrder -8 BackgroundColor "darkGreen" Gain "-Sd" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "V_amp_in" SID "365" Position [635, 118, 665, 132] IconDisplay "Port number" } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "U210V1" DstPort 1 } Line { Name "VLS" Labels [0, 0] SrcBlock "U210V1" SrcPort 1 DstBlock "div. amp.gain factor" DstPort 1 } Line { SrcBlock "U_calc" SrcPort 1 DstBlock "Mms/Sd" DstPort 1 } Line { SrcBlock "Pfb" SrcPort 1 DstBlock "uncoupling\nFB controller" DstPort 1 } Line { SrcBlock "Mms/Sd" SrcPort 1 DstBlock "lead-lag\ncompensator" DstPort 1 } Line { SrcBlock "lead-lag\ncompensator" SrcPort 1 DstBlock "discrete\nderivative" DstPort 1 } Line { SrcBlock "div. amp.gain factor" SrcPort 1 DstBlock "V_amp_in" DstPort 1 } Line { SrcBlock "Sum3" SrcPort 1 DstBlock "Sum1" DstPort 2 } Line { SrcBlock "FLS" SrcPort 1 Points [255, 0] DstBlock "Sum3" DstPort 2 } Line { SrcBlock "discrete\nderivative" SrcPort 1 DstBlock "Sum3" DstPort 1 } Line { SrcBlock "uncoupling\nFB controller" SrcPort 1 Points [20, 0] DstBlock "Sum1" DstPort 1 } Annotation { Name "FLS" Position [305, 129] } } } Block { BlockType Outport Name "chirpsignal" SID "342" Position [750, 218, 780, 232] ZOrder -23 IconDisplay "Port number" } Block { BlockType Outport Name "volts_in" SID "343" Position [300, 133, 330, 147] ZOrder -23 Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "ToAnalogy" SID "150" Position [1020, 148, 1050, 162] BackgroundColor "gray" Port "3" IconDisplay "Port number" } Line { SrcBlock "FromAnalogy" SrcPort 1 DstBlock "volts_in" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Transport\nDelay" DstPort 1 } Line { SrcBlock "Transport\nDelay" SrcPort 1 DstBlock "Switch" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Switch" DstPort 1 } Line { SrcBlock "Switch" SrcPort 1 DstBlock "Amplitude" DstPort 1 } Line { SrcBlock "Chirp" SrcPort 1 Points [25, 0; 0, -30] DstBlock "Switch" DstPort 3 } Line { SrcBlock "Amplitude" SrcPort 1 Points [25, 0] } Line { SrcBlock "Chirp2" SrcPort 1 Points [15, 0] Branch { Points [5, 0] Branch { DstBlock "Amplitude F" DstPort 1 } Branch { Points [0, 85] DstBlock "Amplitude1" DstPort 1 } } Branch { DstBlock "Amplitude U" DstPort 1 } } Line { SrcBlock "Saturation\nfor LS\nprotection" SrcPort 1 DstBlock "ToAnalogy" DstPort 1 } Line { SrcBlock "loudspeaker (&)\naccounting\nfilters (fb&ff)" SrcPort 1 DstBlock "Saturation\nfor LS\nprotection" DstPort 1 } Line { SrcBlock "Amplitude F" SrcPort 1 Points [35, 0] Branch { Points [0, 25; 90, 0] DstBlock "loudspeaker (&)\naccounting\nfilters (fb&ff)" DstPort 3 } Branch { DstBlock "chirpsignal" DstPort 1 } } Annotation { Name "this stuff is not used, but for some reason the real time system is changing the execution timing w" "hen the simulink patch is not complex enough!!" Position [783, 604] } } }